1. Field of the Invention
Systems and methods consistent with the present invention relate to a memory device and a programming method performed therein, and more particularly, to a flash memory system capable of increasing the overall bandwidth and data recording speed by achieving simultaneous performance of sequential transmission of data to each channel unit and storage of data transmitted from a host by using a plurality of buffers, and a programming method performed in the flash memory system.
2. Description of the Related Art
Flash memories, which are non-volatile memories capable of electrically deleting or re-recording data, are classified into a NOR type and a NAND type according to how cells and bitlines are connected to each other.
NAND flash memories, which are storage areas for storing information, include memory cell arrays. A memory cell array includes a plurality of cell strings (which are also called NAND strings). In order to store data in a memory cell array of a flash memory or read data therefrom, the flash memory is provided with a page register circuit. As is well known to those of ordinary skill in the art, memory cells of a NAND flash memory are erased and programmed using a Fowler-Nordheim (F-N) tunneling current.
In order to store data in the memory cell array of the flash memory, first, a write command is given to the flash memory, and addresses and data are consecutively input to the flash memory. Generally, data, which is to be programmed, is sequentially transmitted to a page register circuit on a byte-by-byte basis or on a word-by-word basis. When the to-be-programmed data corresponding to one page of data is completely loaded to the page register circuit, data preserved in the page register circuit is programmed simultaneously in the memory cell array according to a programming command.
In the related art, in order to increase the recording speed of such a flash memory system, a method of programming page data in a plurality of flash memory chips included in each channel according to an interleaving process, or a method of increasing the number of channels and allocating page data to each of the channels has been proposed.
FIG. 1 is a block diagram of a configuration of a related art 2-channel flash memory system 20 using a plurality of flash memory chips. FIG. 2 illustrates a sequence in which data to be recorded in the flash memory system 20 shown in FIG. 1 is transmitted.
Referring to FIG. 1, the related art 2-channel flash memory system 20 includes a host interface unit 21 receiving to-be-recorded data by means of communication with a host 10, a buffer unit 22 storing received data, a control unit 24, and first through fourth flash memory chips 25, 26, 27, and 28. The first and second flash memory chips 25 and 26 constitute a first channel unit CH1, and the third and fourth flash memory chips 27 and 28 constitute a second channel unit CH2.
The host 10 divides the to-be-recorded data into several pieces of data of predetermined size and transmits the divided data. The data received from the host 10 are temporally stored in the buffer unit 22 that is allocated to and stored in the first and second channels CH1 and CH2. For example, referring to FIG. 2, when an 4 Kbyte cluster comprising two pieces of 2 Kbyte page data P1 and P2 is received from the host 10, a first byte of the first page data P1 is allocated to and stored in the first channel unit CH1, and a second byte of the second page data P2 is allocated to and stored in the second channel unit CH2. After the first page data P1 is allocated to and stored in the first channel unit Ch1 and the second channel unit Ch2, each byte of the second page data P2 is allocated to and stored in the first channel unit CH1 and the second channel unit Ch2. More specifically, the first 4 Kbyte cluster data received from the host 10 is allocated to and stored in the first flash memory chip 25 of the first channel unit CH1 and the third flash memory chip 27 of the second channel unit CH2. Then each of the first and second channel units CH1 and CH2 records 2 Kbyte page data to each of the flash memory chips included therein in units of byte, using an interleaving process. During the first 4 Kbyte cluster data is allocated to and stored in the first flash memory chip 25 of the first channel unit CH1 and the third flash memory chip 26 of the second channel unit CH2, the second 4 Kbyte cluster data received from the host 10 is allocated to and stored in the buffers of the second flash memory chip 26 of the first channel unit CH1 and the fourth flash memory chip 28 of the second channel unit CH2. In other words, the interleaving process is performed between the first flash memory chip 25 and the second flash memory chip 26 of the first channel unit CH1, and between the third flash memory chip 27 and the fourth flash memory chip 28 of the second channel unit CH2, respectively. According to this related art, 4 Kbyte data can be recorded during the period of time that 2 Kbyte data is being recorded.
However, in the related art, even when an interleaving process is applied between chips included in the same channel or when the number of the channel is increased, there is a limit as to how much the data recording speed can be improved. When data is recorded to a plurality of memory cell arrays or flash memory chips included in a single channel according to an interleaving process, a bandwidth is limited due to the recording time tWC of the flash memory chip itself. If the recording time tWC of 1 byte data is 25 ns, a possible maximum bandwidth is limited to 40 MB/s (=1 byte/25 ns) even when the bandwidth is improved due to the use of an interleaving process. When the number of channels is increased in order to increase the bandwidth, the size of data being transmitted from a host to a flash memory system increases, leading to an increase in the size of a buffer that temporarily stores the data transmitted by the host. In this case, in order to provide 2 Kbyte page data to each of the channel units CH1 and CH2 of the flash memory system 20, the host 10 should transmit 4 Kbyte data at a time, and the buffer unit 22 should have a size of at least 8 Kbyte for the interleaving process. Also, a cluster gap may be generated due to the increase in size of the unit of a physical data access rate. For example, the host 10 transmits data in units of 8 Kbyte clusters even when data, which is to be actually recorded, is only 2 Kbyte. Accordingly, an empty space is generated in the cluster.